1. Field of the Invention
The present invention relates to a logic circuit, particularly to a read and match circuit for a low-voltage content addressable memory.
2. Description of the Related Art
A content addressable memory (CAM) not only stores data but also compares data. Therefore, a CAM cell not only has circuits for reading and writing data but also has transistors for matching data, wherein the data in the memory array is simultaneously compared with the searched data input externally. The mass parallel comparison operation has an advantage of high speed and a disadvantage of high power consumption.
Refer to FIG. 1 for the architecture of bit lines in a conventional technology. Suppose that Node n1 is at a logic state of 1 and Node n2 is at a logic state of 0 in the memory cell 10, and suppose that the word line WLv is at a logic state of 1 and the bit lines BL and BLn are at a logic state of 1 in a reading activity. The partial voltage will cause a slight voltage rise in Node n2. Thus, the static noise margin is decreased, and the external noise is more likely to affect the stability of the stored data. Once the noise exceeds the allowance, the stored data is damaged.
The influence of current leakage is another problem. Suppose that Node n1, Node n2, Node n3, and Node n4 are respectively at logic states of 1, 0, 0, and 1 in the memory cell 10, and suppose that Node n1 and Node n3 are at a logic state of 0 in the memory cell 12. In a reading activity, the word line WLv is at a logic state of 1, and the bit lines BL and BLn are at a logic state of 1 and at a floating state. The current leakage in the transistor 122 of the memory cell 12 will cause a voltage decrease in the bit line BL, and an error thus occurs.
Refer to FIG. 2 for a NOR-type match-line circuit in a conventional technology. When executing a reading activity at a low voltage, the memory cell 20 also has the problems of static noise margin and bit-line current leakage. The circuit further has a problem that the match line ML is affected by leakage current. Suppose that Node n1 is at a logic state of 1 and Node n2 is at a logic state of 0 in the memory cell 20, and suppose that the search line SL is at a logic state of 1 and the search line SLn is at a logic state of 0. Then, the transistors 201 and 204 are at a conduction state, and the transistors 202 and 203 are at a disconnection state. The current leakage in the transistors 202 and 203 will lower the voltage level of the match line ML, and an error thus occurs.
Accordingly, the present invention proposes a read and match circuit for a low-voltage content addressable memory to overcome the abovementioned problems.